Impact Ionization and Hot-Electron Injection Derived Consistently from Boltzmann Transport

We develop a quantitative model of the impact-ionizationand hot-electron–injection processes in MOS devices from first principles. We begin by modeling hot-electron transport in the drain-to-channel depletion region using the spatially varying Boltzmann transport equation, and we analytically find a self consistent distribution function in a two step process. From the electron distribution function, we calculate the probabilities of impact ionization and hot-electron injection as functions of channel current, drain voltage, and floating-gate voltage. We compare our analytical model results to measurements in long-channel devices. The model simultaneously fits both the hot-electron- injection and impact-ionization data. These analytical results yield an energydependent impact-ionization collision rate that is consistent with numerically calculated collision rates reported in the literature

The matching of small capacitors for analog VLSI

The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 μm×6 μm to 20 μm×20 μm fabricated in a standard 2 μm double-poly CMOS process available through MOSIS. For a size of 6 μm×6 μm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 μm×20 μm size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching

Floating-Gate MOS Synapse Transistors

Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems

An Adaptive WTA using Floating Gate Technology

We have designed, fabricated, and tested an adaptive Winner-Take-All (WTA) circuit based upon the classic WTA of Lazzaro, et al [1]. We have added a time dimension (adaptation) to this circuit to make the input derivative an important factor in winner selection. To accomplish this, we have modified the classic WTA circuit by adding floating gate transistors which slowly null their inputs over time. We present a simplified analysis and experimental data of this adaptive WTA fabricated in a standard CMOS 2µm process

A νMOS soft-maximum current mirror

In this paper, we describe a novel circuit consisting of N+1 MOS transistors and a single floating gate which computes a soft maximum of N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage swing and an interesting feedback mechanism which causes its output impedance to be comparable to that of a normal MOS transistor despite the fact that the output device is a floating-gate transistor

A floating-gate MOS learning array with locally computed weight updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 μs, whereas the weight normalization takes minutes to hours

Scaling pFET Hot-Electron Injection

This paper' elaborates on a previously introduced [l] analytical model for hot-electron injection in pchannel MOSFET's. Hot-electron injection is frequently exploited to remove stored charge in floating-gate circuits. As illustrated in We present data from devices fabricated on processes with minimum channel lengths of 2pm, l p m , 0.5pm, 0.35pm, 0.25pm, O.lSpm, and 0.13pm, modeling these devices analytically in each process. While we can derive the mean free length between phonon collisions, A, using the well known energy of optical phonons in silicon [4], we must provide a theoretical model and experiniental verification of the energy dependence of the mean free lengths between impact-ionization events in the conduction and valence bands, & ( E ) and &+(E)